The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a transistor of a semiconductor device and a method for fabricating the same.
As semiconductor devices are becoming more highly integrated, a method for fabricating a transistor which can secure high current drivability and a short channel margin in a small area emerges as an important matter. Particularly, securing high current drivability is essential for high-speed and low-power devices.
Recently, research for increasing mobility of carriers has been actively conducted to secure high current drivability. A certain level stress is applied to a channel region below a gate to increase the mobility of the carriers. Thus, on-current of a transistor increases. Carriers in P-type metal oxide semiconductor (PMOS) transistor are holes while carriers in N-type MOS (NMOS) transistor are electrons. Thus, the PMOS and the NMOS have different structures for increasing carrier mobility.
FIG. 1 is a cross-sectional view of a structure of a typical PMOS transistor.
Referring to FIG. 1, an isolation layer 11 is formed over a substrate 10 to define an active region.
A gate 12 having a stack structure of a gate insulation layer 12A, a gate electrode 12B, and a gate hard mask layer 12C is formed over the substrate 10. Gate spacers 13 are formed on sidewalls of the gate 12.
Portions of the substrate 10 beside the gate spacers 13 are etched to a certain depth to form a recess R in a source/drain region of the substrate 10. Then, an epitaxial layer 14 is formed to fill the recess R. Since a compressive stress should be applied in a direction parallel to the channel region to increase the mobility of the holes, i.e., carriers, the epitaxial layer 14 includes a material having a larger lattice constant than that of the substrate 10. For instance, when the substrate 10 is a silicon (Si) substrate, the epitaxial layer 14 may include silicon germanium (SiGe) epitaxial layer.
An additive stress may be applied to the channel region by forming a compressive stress layer 15 over a resultant structure including the gate spacers 13 and the epitaxial layer 14.
When the PMOS transistor is fabricated according to the method described above, an epitaxial layer is formed to have the lager lattice constant than that of the substrate in the source/drain region. Thus, the compressive stress is applied in the direction parallel to the channel region, thereby increasing the mobility of the holes.
However, as semiconductor devices are becoming more highly integrated, gate pitch is decreasing. Thus, saturation current (Isat) gain of PMOS transistors is rapidly decreasing (refer to FIG. 2, proposed in an article by S. Tyagi, C. Auth et al, entitled “An Advanced low power high performance, strained channel 65 nm technology”, IEDM, 2005). The area of source/drain regions where the epitaxial layer is formed decreases as the gate pitch deceases. Thus, when it comes to increasing the mobility of the carriers in the PMOS transistor, the typical method illustrated in FIG. 1 is not an effective way to increase current rate.
FIG. 3 is a cross-sectional view of a structure of a typical NMOS transistor.
Referring to FIG. 3, an isolation layer 31 is formed over a substrate 30 to define an active region of the substrate 30.
A gate 32 having a stack structure of a gate insulation layer 32A, a gate electrode 32B, and a gate hard mask layer 32C is formed over the substrate 30. Gate spacers 33 are formed over sidewalls of the gate 32.
A tensile stress layer 34 is formed over a resultant structure including the gate 32 and the gate spacers 33 to induce a lattice mismatch, thereby applying a tensile stress in a direction parallel to a channel region. Thus, the mobility of electrons, i.e., carriers, increases in the NMOS transistor.
However, as semiconductor devices are becoming more highly integrated, gate pitch decreases. Thus, the thickness Tx of the tensile stress layer formed between gates increases, thereby decreasing a stress effect Sxx rapidly (refer to FIG. 4). This is disclosed in an article by A. Oishi, O. Fujii et al, entitled “High performance CMOSFET Technology for 45 nm Generation and Scalability of Stress-Induced Mobility Enhancement Technique”, IEDM, 2005. The typical method illustrated in FIG. 3 also is not an effective way to increase current and increase the mobility of the carriers in the NMOS transistor.
In sum, as semiconductor devices are becoming more highly integrated, the pitch of the gate decreases. Thus, the typical method for forming a filling SiGe epitaxial layer in the source/drain region of a PMOS transistor or the typical method for forming the tensile stress layer over a NMOS transistor exhibits decreased carrier mobility.